On 08/07/2016 07:17 PM, Jaedon Shin wrote:
> Adds NAND device nodes to BCM7xxx MIPS based SoCs.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@xxxxxxxxx>
> ---
> arch/mips/boot/dts/brcm/bcm7125.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7346.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7358.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7360.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7362.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7420.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7425.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7435.dtsi | 20 ++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm7xxx-nand-cs1-bch8.dtsi | 24 ++++++++++++++++++++++
> arch/mips/boot/dts/brcm/bcm97125cbmb.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97358svmb.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97360svmb.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97362svmb.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97420c.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97425svmb.dts | 5 +++++
> arch/mips/boot/dts/brcm/bcm97435svmb.dts | 5 +++++
> 17 files changed, 224 insertions(+)
> create mode 100644 arch/mips/boot/dts/brcm/bcm7xxx-nand-cs1-bch8.dtsi
>
> diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
> index 746ed06c85de..8642631a8451 100644
> --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
> +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
> @@ -226,5 +226,25 @@
> interrupts = <61>;
> status = "disabled";
> };
> +
> + hif_l2_intc: hif_l2_intc@411000 {
> + compatible = "brcm,l2-intc";
> + reg = <0x411000 0x30>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&periph_intc>;
> + interrupts = <0>;
> + };
> +
> + nand: nand@412800 {
> + compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg-names = "nand";
> + reg = <0x412800 0x400>;
> + interrupt-parent = <&hif_l2_intc>;
> + interrupts = <24>;
> + status = "disabled";
> + };
This is a NAND v3.3 controller here not a v5.0 and it uses the EDU
registers for DMA transfers which is not supported in the mainline
driver, so with that dropped, the series looks fine. At any rate this
would require additional brcmnand changes to be supported.
--
Florian
