On Tue, Aug 02, 2016 at 10:29:23AM +0200, Ralf Baechle wrote: > On Thu, May 19, 2016 at 09:38:30AM +0800, Binbin Zhou wrote: > > > diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h > > index b1071c1..f73e671 100644 > > --- a/arch/mips/include/asm/sparsemem.h > > +++ b/arch/mips/include/asm/sparsemem.h > > @@ -11,7 +11,11 @@ > > #else > > # define SECTION_SIZE_BITS 28 > > #endif > > -#define MAX_PHYSMEM_BITS 48 > > +#ifdef CONFIG_64BIT > > +# define MAX_PHYSMEM_BITS 48 > > +#else > > +# define MAX_PHYSMEM_BITS 36 > > +#endif > > This doesn't look right for XPA. What do you think, James? XPA appears to naturally support up to 59 physical address bits, but with a "practical limit" of 40 bits. I haven't quite figured out what the practical limit means to be honest (maybe MIPS32 XPA implementations are simply expected not to exceed 40 bits in practice). So yeh, it should probably be at least 40 when CONFIG_XPA is enabled, although I'm unclear about the consequences. E.g. a bigger MAX_PHYSMEM_BITS increases the number of segment id bits (MAX_PHYSMEM_BITS - SECTION_SIZE_BITS). > > I think we don't use sparsemem on XPA atm so I can apply this safely - > but it should be fixed properly. Right, sparsemem seems to be enabled depending on the platform, so it may only be a matter of time. Cheers James
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