Hi Leonid, On Mon, Jul 11, 2016 at 12:39:03PM -0700, Leonid Yegoshin wrote: > On 07/11/2016 12:21 PM, James Hogan wrote: > > Note also that I have a patch I'm about to submit which changes some of > > those assignments of 0 to assign 1 instead (so as not to confuse the > > cache management code into thinking the CPU has never run the code when > > it has, while still triggering ASID regeneration). That applies here > > too, so it should perhaps be doing something like this instead: > > > > if (t->mm != mm && cpu_context(cpu, t->mm)) > > cpu_context(cpu, t->mm) = 1; > Not sure, but did you have chance to look into having another variable > for cache flush control? It can be that some more states may be needed > in future, so - just disjoin both, TLB and cache coontrol. No, I haven't yet. I'll Cc you so we can discuss there instead, and in the mean time perhaps its best to ignore what I said above for this patch. Cheers James
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