Signed-off-by: Andrea Gelmini <andrea.gelmini@xxxxxxxxx> --- arch/mips/pci/ops-bridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c index 4383194..57e1463 100644 --- a/arch/mips/pci/ops-bridge.c +++ b/arch/mips/pci/ops-bridge.c @@ -33,9 +33,9 @@ static u32 emulate_ioc3_cfg(int where, int size) * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is * not really documented, so right now I can't write code which uses it. * Therefore we use type 0 accesses for now even though they won't work - * correcly for PCI-to-PCI bridges. + * correctly for PCI-to-PCI bridges. * - * The function is complicated by the ultimate brokeness of the IOC3 chip + * The function is complicated by the ultimate brokenness of the IOC3 chip * which is used in SGI systems. The IOC3 can only handle 32-bit PCI * accesses and does only decode parts of it's address space. */ -- 2.8.2.534.g1f66975
