When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Without doing so we default to arbitrarily ignoring all or some subset of interrupts. Signed-off-by: Paul Burton <paul.burton@xxxxxxxxxx> --- arch/mips/kernel/irq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 8eb5af8..f25f7ea 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -54,6 +54,9 @@ void __init init_IRQ(void) for (i = 0; i < NR_IRQS; i++) irq_set_noprobe(i); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + arch_init_irq(); } -- 2.8.2
