On Tue, 10 May 2016, Steven J. Hill wrote:
> The FCSR register is always 32-bits regardless if the platform is
> 32 or 64-bits. Change the type from 'long' to 'int' to reflect this.
> The entire upper half-word of the FCSR register orginally set all
> the bits to 1. Some platforms like the Octeon III simulator will
> actually fault if ones are written to the reserved and/or the FPU
> bits. Correct the mask to avoid this.
This change is broken, see the description of commit 9b26616c8d9d ("MIPS:
Respect the ISA level in FCSR handling") where this code comes from. The
very purpose is to probe for the writability of bits 31:18, in particular
NAN2008 and ABS2008 stuff, but it applies to vendor bits too. An accurate
identification of writable bits is required for the correct presentation
of FCSR via ptrace(2) for programs like GDB.
You need to fix your simulator instead, the architecture does not permit
trapping on optional FCSR bits (there are no reserved bits there anymore
with the current architecture revision) especially as access to this
register is unprivileged. I don't think we can support arbitrary
non-compliant architecture implementations -- if you need to handle an
erratum, then please do it on a PRId by PRId basis.
As to changing the data type, I'm fine in principle, but then please do
so across all our source base where CP1 control registers are handled.
Here the `long' type is used for consistency with the rest of code, so
changing just this single place seems gratuitous to me.
Ralf, please discard this change until it has been corrected.
Maciej
