On Mon, May 09, 2016 at 08:56:51PM +0100, Maciej W. Rozycki wrote: > Yes, but these are not legacy architectures, are they? Since you've got > bits set across Config registers you don't need to resort to poking at > other registers. Although there are exceptions like PABITS and SEGBITS > (we ought to handle this one day actually, for correct unaligned access > emulation -- right now you get a repeated AdEL exception in emulation code > for what originally was an unaligned out of range kernel XKPHYS access, > making it a big pain to debug; I've had a hack for this since 2.4 days, > but it should be done properly). Yeah, it's simply an implementation guided by the SISO principle. Shit in, shit out. The issue you're having rarely hurts and if a simple hack can solve it I'm in principle open to consider it for merging. > In the old days pretty much nothing was recorded in the single Config > register (very old chips didn't even have that -- you had to size caches > manually for example), but stuff could often be determined via other > means, sometimes (like probably here) without detailed checks on PRId. Sizing the R4000/R4400 second level cache for example. I'd call that taking the RISC design principle to the edge :-) Ralf
