On Mon, Apr 18, 2016 at 11:35 AM, Paul Burton <paul.burton@xxxxxxxxxx> wrote:
> There are 2 distinct cases in which a kernel for a MIPS32 CPU
> (CONFIG_CPU_MIPS32=y) may use 64 bit physical addresses
> (CONFIG_PHYS_ADDR_T_64BIT=y):
>
> - 36 bit physical addressing as used by RMI Alchemy & Netlogic XLP/XLR
> CPUs.
>
> - MIPS32r5 eXtended Physical Addressing (XPA).
This hunk here gives me a build failure on Alchemy:
/home/mano/dev/db1200/kernel/linux/arch/mips/mm/init.c: In function
'__kmap_pgprot':
/home/mano/dev/db1200/kernel/linux/arch/mips/mm/init.c:116:28: error:
'_PFNX_MASK' undeclared (first use in this function)
entrylo = (pte.pte_low & _PFNX_MASK);
> diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
> index 5bc663d..58e8bf8 100644
> --- a/arch/mips/include/asm/pgtable-bits.h
> +++ b/arch/mips/include/asm/pgtable-bits.h
> @@ -32,11 +32,11 @@
> * unpredictable things. The code (when it is written) to deal with
> * this problem will be in the update_mmu_cache() code for the r4k.
> */
> -#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
> +#if defined(CONFIG_XPA)
>
> /*
> - * Page table bit offsets used for 64 bit physical addressing on MIPS32,
> - * for example with Alchemy, Netlogic XLP/XLR or XPA.
> + * Page table bit offsets used for 64 bit physical addressing on
> + * MIPS32r5 with XPA.
> */
> enum pgtable_bits {
> /* Used by TLB hardware (placed in EntryLo*) */
> @@ -59,6 +59,27 @@ enum pgtable_bits {
> */
> #define _PFNX_MASK 0xffffff
>
> +#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
> +
> +/*
> + * Page table bit offsets used for 36 bit physical addressing on MIPS32,
> + * for example with Alchemy or Netlogic XLP/XLR.
> + */
> +enum pgtable_bits {
> + /* Used by TLB hardware (placed in EntryLo*) */
> + _PAGE_GLOBAL_SHIFT,
> + _PAGE_VALID_SHIFT,
> + _PAGE_DIRTY_SHIFT,
> + _CACHE_SHIFT,
> +
> + /* Used only by software (masked out before writing EntryLo*) */
> + _PAGE_PRESENT_SHIFT = _CACHE_SHIFT + 3,
> + _PAGE_NO_READ_SHIFT,
> + _PAGE_WRITE_SHIFT,
> + _PAGE_ACCESSED_SHIFT,
> + _PAGE_MODIFIED_SHIFT,
> +};
> +
forgot _PFNX_MASK here?
Manuel
