On Fri, Apr 15, 2016 at 10:22:00PM +0100, James Hogan wrote: > > @@ -1615,9 +1611,8 @@ build_pte_present(u32 **p, struct uasm_reloc **r, > > cur = t; > > } > > uasm_i_andi(p, t, cur, > > - (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT); > > - uasm_i_xori(p, t, t, > > - (_PAGE_PRESENT | _PAGE_READ) >> _PAGE_PRESENT_SHIFT); > > + (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); > > + uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); > > This code makes the assumption that _PAGE_READ was always at a higher > bit number than _PAGE_PRESENT, however this isn't true for _PAGE_NO_READ > in the defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) > case, where the no read bit will have been shifted off the end of the > register value. Hi James, Note that as of this patch the PHYS_ADDR_T_64BIT && CPU_MIPS32 case is still the XPA case, until patch 7. XPA support hardcodes for RIXI being present, which whilst technically doesn't seem valid it's already in mainline & seems like a requirement unlikely to be violated - R6 mandates RIXI, and it seems unlikely any new R5 + XPA cores would come along at this point. That being the case, XPA kernels where _PAGE_PRESENT_SHIFT > _PAGE_NO_READ_SHIFT would always take the cpu_has_rixi path & not hit the problem you describe, or else would already be hitting problems elsewhere due to the lack of RIXI. I agree it would be good to make that clearer though, so will add a panic or something in another patch. > Other than that, I can't fault this patch. Thanks for the review :) Paul
