Loongson-3 maintains cache coherency by hardware, this means: 1) Loongson-3's icache is coherent with dcache. 2) Loongson-3's dcaches don't alias (if PAGE_SIZE>=16K). 3) Loongson-3 maintains cache coherency across cores (and for DMA). Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx> --- arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index c3406db..647d952 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -46,6 +46,7 @@ #define cpu_has_local_ebase 0 #define cpu_has_wsbh IS_ENABLED(CONFIG_CPU_LOONGSON3) +#define cpu_has_coherent_cache IS_ENABLED(CONFIG_CPU_LOONGSON3) #define cpu_hwrena_impl_bits 0xc0000000 #endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */ -- 2.7.0 3h?
