On 09/02/16 12:55, Florian Fainelli wrote:
> Disable pref 30 by utilizing the standard quirk method and matching the
> affected SoCs: 7344, 7436, 7425.
>
> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx>
> ---
> arch/mips/bmips/setup.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
> index 35535284b39e..9c8f15daf5e9 100644
> --- a/arch/mips/bmips/setup.c
> +++ b/arch/mips/bmips/setup.c
> @@ -100,12 +100,28 @@ static void bcm6368_quirks(void)
> bcm63xx_fixup_cpu1();
> }
>
> +static void bmips5000_pref30_quirk(void)
> +{
> + __asm__ __volatile__(
> + " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
> + " lui $9, 0x0100\n"
> + " or $8, $9\n"
> + /* disable "pref 30" on buggy CPUs */
> + " lui $9, 0x0800\n"
> + " or $8, $9\n"
> + " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
> + : : : "$8", "$9");
We are missing an additional load here to $8, I will respin this patch,
but would appreciate feedback on the other patches of the series so I
can address everything at once. Thanks!
> +}
> +
> static const struct bmips_quirk bmips_quirk_list[] = {
> { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
> { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
> { "brcm,bcm6328", &bcm6328_quirks },
> { "brcm,bcm6368", &bcm6368_quirks },
> { "brcm,bcm63168", &bcm6368_quirks },
> + { "brcm,bcm7344", &bmips5000_pref30_quirk },
> + { "brcm,bcm7346", &bmips5000_pref30_quirk },
> + { "brcm,bcm7425", &bmips5000_pref30_quirk },
> { },
> };
>
>
--
Florian
