Currently only the UART, SPI-flash and LEDs are supported. Please see https://onion.io/omega for details. Signed-off-by: Antony Pavlov <antonynpavlov@xxxxxxxxx> Cc: Gabor Juhos <juhosg@xxxxxxxxxxx> Cc: Alban Bedel <albeu@xxxxxxx> Cc: L. D. Pinney <ldpinney@xxxxxxxxx> Cc: Boken Lin <bl@xxxxxxxx> Cc: Jacky Huang <huangfangcheng@xxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx Cc: devicetree@xxxxxxxxxxxxxxx --- arch/mips/ath79/Kconfig | 5 ++++ arch/mips/boot/dts/qca/Makefile | 1 + arch/mips/boot/dts/qca/omega.dts | 54 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 2797581..5273039 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -82,6 +82,11 @@ choice select BUILTIN_DTB select SOC_AR933X + config DTB_ONION_OMEGA + bool "Onion Omega" + select BUILTIN_DTB + select SOC_AR933X + config DTB_TL_MR3020 bool "TL-MR3020" select BUILTIN_DTB diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile index 428ebac5..efecdac 100644 --- a/arch/mips/boot/dts/qca/Makefile +++ b/arch/mips/boot/dts/qca/Makefile @@ -1,6 +1,7 @@ # All DTBs dtb-$(CONFIG_DTB_TL_WR1043ND_V1) += ar9132_tl_wr1043nd_v1.dtb dtb-$(CONFIG_DTB_DRAGINO_MS14) += dragino_ms14.dtb +dtb-$(CONFIG_DTB_ONION_OMEGA) += omega.dtb dtb-$(CONFIG_DTB_TL_MR3020) += tl_mr3020.dtb obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y)) diff --git a/arch/mips/boot/dts/qca/omega.dts b/arch/mips/boot/dts/qca/omega.dts new file mode 100644 index 0000000..9cd9f91 --- /dev/null +++ b/arch/mips/boot/dts/qca/omega.dts @@ -0,0 +1,54 @@ +/dts-v1/; + +#include "ar9331.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Onion Omega"; + compatible = "onion,omega"; + + aliases { + serial0 = &uart; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + + system { + label = "onion:amber:system"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&extosc { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Winbond 25Q128FVSG SPI flash */ + spiflash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; -- 2.6.2
