On Tue, 12 Jan 2016, Ralf Baechle wrote: > > We could do better though, by having a register stash area defined > > somewhere in low memory (0x0-0x7fff) -- of course if physical memory is > > actually available there in a given system. Remember that setting > > CP0.Status.ERL makes KUSEG identity mapped, making it possible to access > > its beginning off $zero and save all GPRs in a non-destructive manner. > > > > That is however assuming we can take control at all in the first place as > > the NMI vector is hardwired and points to a ROM location in a typical > > system. > > NMIs don't nest; the system is lost if it receives another NMI before the > state of the first is saved. It's currently up to the system to avoid that > probably by yes masking the non-maskable interrupt. Indeed, ErrorEPC will be lost on a nested NMI. We should be able to detect it and let the handler complete gracefully if it reaches to the end uninterrupted. > ErrorEPC is also used by cache errors so an NMI following a cache error > exception before state has been saved might be fatal. Hmm, I think a cache error is fatal by itself, so this scenario is probably not of much concern -- just dumping the available state to the console and panicking should do. > These are scenarios that are taken care of by CISC architectures but on a > purebred RISC they're up to system implementors. E.g. x86 masks NMIs internally to avoid nesting, but it is able to notice another incoming NMI and releases it as soon as the handling of the previous one has completed. We'd need to have external circuitry for any handling of this kind. Maciej
