[PATCH 3/6] MIPS: Loongson-3: Fix SMP_ASK_C0COUNT IPI handler

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



When Core-0 handle SMP_ASK_C0COUNT IPI, we should make other cores to
see the result as soon as possible (especially when Store-Fill-Buffer
is enabled). Otherwise, C0_Count syncronization makes no sense.

BTW, there is a corner should be avoid: C0_Count of Core-0 is really 0.

Cc: <stable@xxxxxxxxxxxxxxx>
Signed-off-by: Huacai Chen <chenhc@xxxxxxxxxx>
---
 arch/mips/loongson64/loongson-3/smp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/loongson-3/smp.c
index 1a4738a..55d0f5f 100644
--- a/arch/mips/loongson64/loongson-3/smp.c
+++ b/arch/mips/loongson64/loongson-3/smp.c
@@ -275,8 +275,10 @@ void loongson3_ipi_interrupt(struct pt_regs *regs)
 	if (action & SMP_ASK_C0COUNT) {
 		BUG_ON(cpu != 0);
 		c0count = read_c0_count();
+		c0count = c0count ? c0count : 1;
 		for (i = 1; i < num_possible_cpus(); i++)
 			per_cpu(core0_c0count, i) = c0count;
+		__wbflush(); /* Let others see the result ASAP */
 	}
 }
 
-- 
2.4.6



ÿÿ		




[Index of Archives]     [Linux MIPS Home]     [LKML Archive]     [Linux ARM Kernel]     [Linux ARM]     [Linux]     [Git]     [Yosemite News]     [Linux SCSI]     [Linux Hams]

  Powered by Linux