Hi. I just wanted to confirm that this is the right list for this kind of patches. Please let me know if I should submit it to some other place. Thanks! 2015-12-08 13:27 GMT-05:00 Nikolay Martynov <mar.kolya@xxxxxxxxx>: > According to 'MIPS32® interAptivTM Multiprocessing > System Programmer’s Guide' CPC_BASE_ADDR takes bits [31:15]. > > This change is tested ith mt7621 which wasn't working without it. > > Signed-off-by: Nikolay Martynov <mar.kolya@xxxxxxxxx> > --- > arch/mips/include/asm/mips-cm.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h > index 6516e9d..f942ec2 100644 > --- a/arch/mips/include/asm/mips-cm.h > +++ b/arch/mips/include/asm/mips-cm.h > @@ -286,8 +286,8 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) > #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) > > /* GCR_CPC_BASE register fields */ > -#define CM_GCR_CPC_BASE_CPCBASE_SHF 17 > -#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) > +#define CM_GCR_CPC_BASE_CPCBASE_SHF 15 > +#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x1ffff) << 15) > #define CM_GCR_CPC_BASE_CPCEN_SHF 0 > #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) > > -- > 2.6.3 > -- Martynov Nikolay. Email: mar.kolya@xxxxxxxxx
