On Thu, Dec 10, 2015 at 09:49:21PM +0000, Simon Arlott wrote:
> Add device tree binding for the BCM6345's gated clocks.
>
> The BCM6345 contains clocks gated with a register. Clocks are indexed
> by bits in the register and are active high. Most MIPS-based BCM63xx
> SoCs have a clock gating set of registers, but some have clock gate bits
> interleaved with other status bits and configurable clocks in the same
> register.
>
> Signed-off-by: Simon Arlott <simon@xxxxxxxxxxx>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
> ---
> v2: Added clock-indices, clock-output-names (from clock-bindings.txt),
> these are required properties.
>
> v1: Renamed from BCM63xx to BCM6345.
>
> .../bindings/clock/brcm,bcm6345-gate-clk.txt | 62 ++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm6345-gate-clk.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm6345-gate-clk.txt b/Documentation/devicetree/bindings/clock/brcm,bcm6345-gate-clk.txt
> new file mode 100644
> index 0000000..a6e264c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/brcm,bcm6345-gate-clk.txt
> @@ -0,0 +1,62 @@
> +Broadcom BCM6345 clocks
> +
> +This binding uses the common clock binding:
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +The BCM6345 contains clocks gated with a register. Clocks are indexed
> +by bits in the register and are active high. Most MIPS-based BCM63xx
> +SoCs have a clock gating set of registers, but some have clock gate bits
> +interleaved with other status bits and configurable clocks in the same
> +register.
> +
> +Required properties:
> +- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm6345-gate-clk"
> +- #clock-cells: Should be <1>.
> +- regmap: The register map phandle
> +- offset: Offset in the register map for the clock register (in bytes)
> +- clocks: The external oscillator clock phandle
> +- clock-indices: The bits in the register used for gated clocks.
> +- clock-output-names: Should be a list of strings of clock output signal
> + names indexed by the clock indices.
> +
> +Example:
> +
> +periph_clk: periph_clk {
> + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm6345-gate-clk";
> + regmap = <&periph_cntl>;
> + offset = <0x4>;
> +
> + #clock-cells = <1>;
> + clock-indices =
> + <1>, <2>, <3>, <4>, <5>,
> + <6>, <7>, <8>, <9>, <10>,
> + <11>, <12>, <13>, <14>, <15>,
> + <16>, <17>, <18>, <19>, <20>,
> + <27>, <31>;
> + clock-output-names =
> + "vdsl_qproc", "vdsl_afe", "vdsl", "mips", "wlan_ocp",
> + "dect", "fap0", "fap1", "sar", "robosw",
> + "pcm", "usbd", "usbh", "ipsec", "spi",
> + "hsspi", "pcie", "phymips", "gmac", "nand",
> + "tbus", "robosw250";
> +};
> +
> +timer_clk: timer_clk {
> + compatible = "brcm,bcm63168-gate-clk", "brcm,bcm6345-gate-clk";
> + regmap = <&timer_cntl>;
> + offset = <0x4>;
> +
> + #clock-cells = <1>;
> + clock-indices = <17>, <18>;
> + clock-output-names = "uto_extin", "usb_ref";
> +};
> +
> +ehci0: usb@10002500 {
> + compatible = "brcm,bcm63168-ehci", "brcm,bcm6345-ehci", "generic-ehci";
> + reg = <0x10002500 0x100>;
> + big-endian;
> + interrupt-parent = <&periph_intc>;
> + interrupts = <10>;
> + clocks = <&periph_clk 13>, <&timer_clk 18>;
> + phys = <&usbh>;
> +};
> --
> 2.1.4
>
> --
> Simon Arlott
