When estimating the clock frequency based on the RTC, the Update In Progress flag is used to wait one second. However, the logic waiting for the falling edge of this signal was inverted such that any read of the RTC registers may actually occur during the update window and be undefined. Signed-off-by: Matt Redfearn <matt.redfearn@xxxxxxxxxx> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Cc: Steven J. Hill <Steven.Hill@xxxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx --- arch/mips/mti-malta/malta-time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c index 67eff9ed157c..3b97cfd0cf4c 100644 --- a/arch/mips/mti-malta/malta-time.c +++ b/arch/mips/mti-malta/malta-time.c @@ -84,8 +84,8 @@ static void __init estimate_frequencies(void) local_irq_save(flags); /* Start counter exactly on falling edge of update flag. */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + while (CMOS_READ(RTC_REG_A) & RTC_UIP); /* Initialize counters. */ start = read_c0_count(); @@ -96,8 +96,8 @@ static void __init estimate_frequencies(void) secs1 = CMOS_READ(RTC_SECONDS); /* Read counter exactly on falling edge of update flag. */ - while (CMOS_READ(RTC_REG_A) & RTC_UIP); while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); + while (CMOS_READ(RTC_REG_A) & RTC_UIP); count = read_c0_count(); if (gic_present) -- 2.1.4
