On 23/11/15 18:19, Florian Fainelli wrote: > On 23/11/15 07:02, Jonas Gorski wrote: >> On Sun, Nov 22, 2015 at 3:07 PM, Simon Arlott <simon@xxxxxxxxxxx> wrote: >>> -#define WDT_HZ 50000000 /* Fclk */ >>> +#define WDT_CLK_NAME "periph" >> >> @Florian: >> Is this correct? The comment for the watchdog in 6358_map_part.h and >> earlier claims that the clock is 40 MHz there, but the code uses 50MHz >> - is this a bug in the comments or is it a bug taken over from the >> original broadcom code? I'm sure that the periph clock being 50 MHz >> even on the older chips is correct, else we'd have noticed that in >> serial output (where it's also used). > > There are references to a Fbus2 clock in documentation, but I could not > find any actual documentation for its actual clock frequency, I would be > surprised if this chip would have diverged from the previous and future > ones and used a 40Mhz clock. 6345 started with a peripheral clock > running at 50Mhz, and that is true for all chips since then AFAICT. > > I agree we would have noticed this with the UART or SPI controllers if > that was not true, so probably a code glitch here... I've tested both the timer and the watchdog and they give near perfect time intervals (within 1-2ms based on printk times over serial) so it'd be obvious if they were out by 25%. -- Simon Arlott
