On Fri, Oct 30, 2015 at 11:01:17PM +0900, Jaedon Shin wrote:
> Add quirk for phy interface of MIPS-based chipsets. The ARM-based
> chipsets have four phy interface control registers and each port has two
> registers but the MIPS-based chipsets have three. There are no
> information and documentation.
>
> The Broadcom strict-ahci based BSP of legacy version did not control
> these registers.
...
> enum brcm_ahci_quirks {
> BRCM_AHCI_QUIRK_NONCQ = BIT(0),
> + BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
> };
I see. There's another quirk flag which actually needs to be
persistent. Hmm... I don't know. Ah well, please disregard my
previous comment.
Thanks.
--
tejun
