On Tue, 17 Nov 2015, Qais Yousef wrote:
> On 11/16/2015 05:17 PM, Thomas Gleixner wrote:
> > On Mon, 9 Nov 2015, Qais Yousef wrote:
> > > On 11/07/2015 02:51 PM, Thomas Gleixner wrote:
> > > Generally it's hard to know whether a real device is connected to a hwirq
> > > or
> > > not. I am saving a patch where we get a set of free hwirqs from DT as only
> > > the
> > > SoC designer knows what hwirq are actually free and safe to use for IPI.
> > > I'll
> > > send this patch with the DT IPI changes or the rproc driver that I will be
> > > send once these changes are merged.
> > >
> > > The current code assumes that the last 2 * NR_CPUs hwirqs are always free
> > > to
> > > use for Linux SMP.
> > So what you're saying is that you cannot rely on the last X hwirqs
> > being available for IPIs. That's insane and to my knowledge there is
> > no hardware out there which does not reserve a consecutive IPI space.
>
> If I read the code you were suggesting correctly, you were trying to fit the
> IPIs in any available non allocated area in the GIC space. What I am trying to
> say is that we can only work on a limited subset of this space that we are
> told explicitly it's safe to use for IPIs. Most likely it's consecutive, but I
> don't feel brave enough to make this assumption personally - maybe I'm over
> paranoid.. I'm more keen on anything that would simplify this patch series now
> though.
Right, I was assuming a consecutive available space and your hardware
folks should really avoid to break that assumption.
Now you still need some DT support to describe the space which is
available for IPIs and that should be part of that series.
> I'll do my best with the next series but maybe we'd need to iterate
> this more than once till I get it right.
Thanks for being patient and persistant on that!
tglx
