On Sat, Sep 12, 2015 at 08:11:31AM -0700, Paul Burton wrote: > Date: Sat, 12 Sep 2015 08:11:31 -0700 > From: Paul Burton <paul.burton@xxxxxxxxxx> > To: Ralf Baechle <ralf@xxxxxxxxxxxxxx> > CC: linux-mips@xxxxxxxxxxxxxx, Markos Chandras > <markos.chandras@xxxxxxxxxx>, stable@xxxxxxxxxxxxxxx, > linux-kernel@xxxxxxxxxxxxxxx > Subject: Re: [PATCH 5/6] MIPS: CONFIG_MIPS_MT_SMP should depend upon > CPU_MIPSR2 > Content-Type: text/plain; charset="utf-8" > > On Sat, Sep 12, 2015 at 12:16:39PM +0200, Ralf Baechle wrote: > > > config MIPS_MT_SMP > > > bool "MIPS MT SMP support (1 TC on each available VPE)" > > > - depends on SYS_SUPPORTS_MULTITHREADING > > > + depends on SYS_SUPPORTS_MULTITHREADING && CPU_MIPSR2 > > > > Right now this line is > > > > depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 > > > > which I believe is correct. The MT SMP support aka VSMP had been > > carefully crafted to work on older ASEs that is all use of MIPS MT > > instructions or features was carefully protected by cpu_has_mipsmt > > or similar. > > I disagree. The "background" section in the introduction to the MT ASE > spec (MD00376, revision 1.12) reads: > > > Multi-threading, or the concurrent presence of multiple active threads > > or contexts of execution on the same CPU, is an increasingly > > widely-used technique for tolerating memory and execution latency and > > for getting higher utilization out of processor functional units. The > > MIPS® Multi-threading (MT) Module is an extension to Release 2 (and > > newer) of the MIPS32® Architecture which provides a framework for > > multi-threading the MIPS processor architecture. > > MT is quite clearly an extension to r2. The MT bit in Config3 has this > note in the MIPS32 PRA (MD00088, revision 6.01): > > > For Release 6 and MIPS after, this bit must be 0. > > Thus MT is an option from r2 <= ISA < r6. The current !CPU_MIPSR6 > constraint in Kconfig only enforces half of that. Depending upon > CPU_MIPSR2 would enforce the whole. Correct. Still, VSMP's use of MT instruction is very limited to a few particular places in the kernel which makes a simple exervise to support a kernel that is capable of supporting VSMP yet will support MIPS IV, MIPS 32R1 CPUs or MIPS 32R2+ without MT. Ralf
