From: Hauke Mehrtens <hauke.mehrtens@xxxxxxxxxx>
From: Hauke Mehrtens <hauke.mehrtens@xxxxxxxxxx>
This register is also used on other SoCs.
Signed-off-by: Hauke Mehrtens <hauke.mehrtens@xxxxxxxxxx>
---
arch/mips/lantiq/xway/clk.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index 8750dc0..e9e0d1f 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -25,8 +25,8 @@ static unsigned int ram_clocks[] = {
/* legacy xway clock */
#define CGU_SYS 0x10
-/* vr9 clock */
-#define CGU_SYS_VR9 0x0c
+/* vr9, ar10/grx390 clock */
+#define CGU_SYS_XRX 0x0c
#define CGU_IF_CLK_VR9 0x24
unsigned long ltq_danube_fpi_hz(void)
@@ -104,7 +104,7 @@ unsigned long ltq_vr9_cpu_hz(void)
unsigned int cpu_sel;
unsigned long clk;
- cpu_sel = (ltq_cgu_r32(CGU_SYS_VR9) >> 4) & 0xf;
+ cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf;
switch (cpu_sel) {
case 0:
@@ -145,7 +145,7 @@ unsigned long ltq_vr9_fpi_hz(void)
unsigned long clk;
cpu_clk = ltq_vr9_cpu_hz();
- ocp_sel = ltq_cgu_r32(CGU_SYS_VR9) & 0x3;
+ ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3;
switch (ocp_sel) {
case 0:
--
2.6.1
