On Tue, Aug 18, 2015 at 2:32 AM, Govindraj Raja
<govindraj.raja@xxxxxxxxxx> wrote:
> From: Zdenko Pulitika <zdenko.pulitika@xxxxxxxxxx>
>
> .recalc_rate callback for the fractional PLL doesn't take operating
> mode into account when calculating PLL rate. This results in
> the incorrect PLL rates when PLL is operating in integer mode.
>
> Operating mode of fractional PLL is based on the value of the
> fractional divider. Currently it assumes that the PLL will always
> be configured in fractional mode which may not be
> the case. This may result in the wrong output frequency.
>
> Also vco was calculated based on the current operating mode which
> makes no sense because .set_rate is setting operating mode. Instead,
> vco should be calculated using PLL settings that are about to be set.
>
> Signed-off-by: Zdenko Pulitika <zdenko.pulitika@xxxxxxxxxx>
> Signed-off-by: Govindraj Raja <govindraj.raja@xxxxxxxxxx>
One minor comment below, otherwise:
Reviewed-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> --- a/drivers/clk/pistachio/clk-pll.c
> +++ b/drivers/clk/pistachio/clk-pll.c
> @@ -65,6 +65,10 @@
> #define MIN_OUTPUT_FRAC 12000000UL
> #define MAX_OUTPUT_FRAC 1600000000UL
>
> +/* Fractional PLL operating modes */
> +#define PLL_MODE_INT 1
> +#define PLL_MODE_FRAC 0
Make this an enum (e.g. enum pll_mode) and ...
> +static inline u32 pll_frac_get_mode(struct clk_hw *hw)
> +{
> + struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
> + u32 val;
> +
> + val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;
> + return val ? PLL_MODE_INT : PLL_MODE_FRAC;
> +}
> +
> +static inline void pll_frac_set_mode(struct clk_hw *hw, u32 mode)
> +{
> + struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
> + u32 val;
> +
> + val = pll_readl(pll, PLL_CTRL3);
> + if (mode == PLL_MODE_INT)
> + val |= PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD;
> + else
> + val &= ~(PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_DACPD);
> +
> + pll_writel(pll, val, PLL_CTRL3);
> +}
... use the enum type instead of u32 for the mode.
