On 07/14/2015 01:40 PM, Paul Burton wrote: >> @@ -152,7 +152,7 @@ dcache_done: >> >> /* Enter the coherent domain */ >> li t0, 0xff >> - sw t0, GCR_CL_COHERENCE_OFS(v1) >> + PTR_S t0, GCR_CL_COHERENCE_OFS(v1) > > Hi Markos, > > I don't believe this is correct where accessing GCRs. Since you've > pushed elsewhere to perform 32 bit accesses when running a 32 bit kernel > on a MIPS64 core with CM3, can we just keep doing 32 bit accesses here? > Hi Paul, Yes. This patch is already upstream though. I will wait for the 'mips_cm_is64' to make it upstream as well and then I will submit a fix for this one. It should not break anything at the moment. Thanks -- markos
