On Tue, Apr 21, 2015 at 03:46:53PM +0100, Paul Burton wrote:
> Migrate the JZ4740 & the qi_lb60 board to use common clock framework
> via the new Ingenic SoC CGU driver.
Maybe worth mentioning that debugfs interface removed because common
clock framework already provides something similar.
> +static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
> +
> + /* External clocks */
> +
> + [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
> + [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
> +
> + [JZ4740_CLK_PLL] = {
> + "pll", CGU_CLK_PLL,
> + .parents = { JZ4740_CLK_EXT, -1 },
I thought parents had 4 elements. Do the other two need initialising to -1 (and
below).
> + .pll = {
> + .reg = CGU_REG_CPPCR,
> + .m_shift = 23,
> + .m_bits = 9,
> + .m_offset = 2,
> + .n_shift = 18,
> + .n_bits = 5,
> + .n_offset = 2,
> + .od_shift = 16,
> + .od_bits = 2,
> + .od_max = 4,
> + .od_encoding = pll_od_encoding,
> + .stable_bit = 10,
> + .bypass_bit = 9,
> + .enable_bit = 8,
> + },
> + },
> +
> + /* Muxes & dividers */
> +
> + [JZ4740_CLK_PLL_HALF] = {
> + "pll half", CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_PLL, -1 },
> + .div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 },
> + },
> +
> + [JZ4740_CLK_CCLK] = {
> + "cclk", CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_PLL, -1 },
> + .div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 },
> + },
> +
> + [JZ4740_CLK_HCLK] = {
> + "hclk", CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_PLL, -1 },
> + .div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 },
> + },
> +
> + [JZ4740_CLK_PCLK] = {
> + "pclk", CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_PLL, -1 },
> + .div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 },
> + },
> +
> + [JZ4740_CLK_MCLK] = {
> + "mclk", CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_PLL, -1 },
> + .div = { CGU_REG_CPCCR, 12, 4, 22, -1, -1 },
> + },
> +
> + [JZ4740_CLK_LCD] = {
> + "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_PLL_HALF, -1 },
> + .div = { CGU_REG_CPCCR, 16, 5, 22, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 10 },
> + },
> +
> + [JZ4740_CLK_LCD_PCLK] = {
> + "lcd_pclk", CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_PLL_HALF, -1 },
> + .div = { CGU_REG_LPCDR, 0, 11, -1, -1, -1 },
> + },
> +
> + [JZ4740_CLK_I2S] = {
> + "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1 },
> + .mux = { CGU_REG_CPCCR, 31, 1 },
> + .div = { CGU_REG_I2SCDR, 0, 8, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 6 },
> + },
> +
> + [JZ4740_CLK_SPI] = {
> + "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1 },
> + .mux = { CGU_REG_SSICDR, 31, 1 },
> + .div = { CGU_REG_SSICDR, 0, 4, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 4 },
> + },
> +
> + [JZ4740_CLK_MMC] = {
> + "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_PLL_HALF, -1 },
> + .div = { CGU_REG_MSCCDR, 0, 5, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 7 },
> + },
> +
> + [JZ4740_CLK_UHC] = {
> + "uhc", CGU_CLK_DIV | CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_PLL_HALF, -1 },
> + .div = { CGU_REG_UHCCDR, 0, 4, -1, -1, -1 },
> + .gate = { CGU_REG_CLKGR, 14 },
> + },
> +
> + [JZ4740_CLK_UDC] = {
> + "udc", CGU_CLK_MUX | CGU_CLK_DIV,
> + .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1 },
> + .mux = { CGU_REG_CPCCR, 29, 1 },
> + .div = { CGU_REG_CPCCR, 23, 6, -1, -1, -1 },
> + .gate = { CGU_REG_SCR, 6 },
> + },
> +
> + /* Gate-only clocks */
> +
> + [JZ4740_CLK_UART0] = {
> + "uart0", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, -1 },
> + .gate = { CGU_REG_CLKGR, 0 },
> + },
> +
> + [JZ4740_CLK_UART1] = {
> + "uart1", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, -1 },
> + .gate = { CGU_REG_CLKGR, 15 },
> + },
> +
> + [JZ4740_CLK_DMA] = {
> + "dma", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_PCLK, -1 },
> + .gate = { CGU_REG_CLKGR, 12 },
> + },
> +
> + [JZ4740_CLK_IPU] = {
> + "ipu", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_PCLK, -1 },
> + .gate = { CGU_REG_CLKGR, 13 },
> + },
> +
> + [JZ4740_CLK_ADC] = {
> + "adc", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, -1 },
> + .gate = { CGU_REG_CLKGR, 8 },
> + },
> +
> + [JZ4740_CLK_I2C] = {
> + "i2c", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, -1 },
> + .gate = { CGU_REG_CLKGR, 3 },
> + },
> +
> + [JZ4740_CLK_AIC] = {
> + "aic", CGU_CLK_GATE,
> + .parents = { JZ4740_CLK_EXT, -1 },
> + .gate = { CGU_REG_CLKGR, 5 },
> + },
> +};
> +
> +static void __init jz4740_cgu_init(struct device_node *np)
> +{
> + int retval;
> +
> + cgu = ingenic_cgu_new(jz4740_cgu_clocks,
> + ARRAY_SIZE(jz4740_cgu_clocks), np);
> + if (!cgu)
> + pr_err("%s: failed to initialise CGU\n", __func__);
return, to avoid passing NULL to ingenic_cgu_register_clocks?
> +
> + retval = ingenic_cgu_register_clocks(cgu);
> + if (retval)
> + pr_err("%s: failed to register CGU Clocks\n", __func__);
> +}
> +CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
Cheers
James
Attachment:
signature.asc
Description: Digital signature
