Hi James. On Fri, Apr 17, 2015 at 2:44 AM, James Hogan <james.hogan@xxxxxxxxxx> wrote: > Wider testing reveals that the Fast Debug Channel (FDC) interrupt is > routed through the GIC just fine on Pistachio SoC, even though it > contains interAptiv cores. Clearly the FDC interrupt routing problems > previously observed on interAptiv and proAptiv cores are specific to the > Malta FPGA bitstreams. > > Move the workaround for interAptiv and proAptiv out of > gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's > get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use > the FDC interrupt. > > Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx> Reviewed-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
