On Wed, 11 Mar 2015, James Hogan wrote: > When handling floating point exceptions (FPEs) and MSA FPEs the Cause > bits of the appropriate control and status register (FCSR for FPEs and > MSACSR for MSA FPEs) are read and cleared before enabling interrupts, > presumably so that it doesn't have to go through the pain of restoring > those bits if the process is pre-empted, since writing those bits would > cause another immediate exception while still in the kernel. Another reason is MIPS I processors (and for the record I believe the R6000 MIPS II implementation as well) signal FPA exceptions using an ordinary interrupt, seen on one of the IP[7:2] bits in the CP0 Cause register. Consequently reenabling interrupts without first clearing at least all the unmasked FCSR.Cause bits would retrigger the interrupt and cause an infinite loop. We don't ever mask the FPA interrupt with the relevant IM[7:2] bit in the CP0 Status register, because for simplicity we reuse the whole of the FPE exception handling path for FPA interrupts as well. Except that we enter it via the `handle_fpe_int' alternative entry point rather than the usual `handle_fpe' one, bypassing the register save sequence as it was already done by the interrupt handler. Maciej
