On Sun, Nov 16, 2014 at 01:02:29AM +0000, Maciej W. Rozycki wrote: > Fix the 74K D-cache alias erratum workaround so that it actually works. > Our current code sets MIPS_CACHE_VTAG for the D-cache, but that flag > only has any effect for the I-cache. Additionally MIPS_CACHE_PINDEX is > set for the D-cache if CP0.Config7.AR is also set for an affected > processor, leading to confusing information in the bootstrap log (the > flag isn't used beyond that). > > So delete the setting of MIPS_CACHE_VTAG and rely on MIPS_CACHE_ALIASES, > set in a common place, removing I-cache coherency issues seen in GDB > testing with software breakpoints, gdbserver and ptrace(2), on affected > systems. > > While at it add a little piece of explanation of what CP0.Config6.SYND > is so that people do not have to chase documentation. > > Signed-off-by: Maciej W. Rozycki <macro@xxxxxxxxxxxxxxxx> > --- > Hi, > > It looks like I-cache aliasing handling setup needs some TLC too, first > of all what's the purpose of checking CP0.Config7.IAR and setting the > MIPS_CACHE_ALIASES flag for the I-cache where the flag is nowhere used > afterwards? Anyway that's something for another occasion. For now, > please apply this change. Applied, finally. I take it the discussion in https://patchwork.linux-mips.org/patch/8876/ does not concern the correctness of your patch. Backporting this patch to older kernels is getting increasingly more painful so I only did so for kernels as old as 3.13. If anybody cares, send patches :) Thanks Maciej! Ralf
