Hi, On Tue, Mar 31, 2015 at 6:25 PM, Bert Vermeulen <bert@xxxxxxxx> wrote: > This driver mediates access between the connected CPLD and other devices > on the bus. > > The m25p80-compatible boot flash and (some models) MMC use regular SPI, > bitbanged as required by the SoC. However the SPI-connected CPLD has > a "fast write" mode, in which two bits are transferred by SPI clock > cycle. The second bit is transmitted with the SoC's CS2 pin. > > Protocol drivers using this fast write facility signal this by setting > the cs_change flag on transfers. > > Signed-off-by: Bert Vermeulen <bert@xxxxxxxx> > --- > drivers/spi/Kconfig | 6 ++ > drivers/spi/Makefile | 1 + > drivers/spi/spi-rb4xx.c | 244 ++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 251 insertions(+) > create mode 100644 drivers/spi/spi-rb4xx.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index ab8dfbe..aa76ce5 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -429,6 +429,12 @@ config SPI_ROCKCHIP > The main usecase of this controller is to use spi flash as boot > device. > > +config SPI_RB4XX > + tristate "Mikrotik RB4XX SPI master" > + depends on SPI_MASTER && ATH79_MACH_RB4XX There is no ATH79_MACH_RB4XX in upstream. I suggest depending on just ATH79, allowing maintainers/patch submitters to at least test build any future modifications on it. Regards Jonas
