On Fri, Mar 27, 2015 at 5:04 AM, Ralf Baechle <ralf@xxxxxxxxxxxxxx> wrote: > On Wed, Mar 25, 2015 at 09:55:14PM -0700, Florian Fainelli wrote: > >> From: Kevin Cernekee <cernekee@xxxxxxxxx> >> >> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from >> the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer >> may cause parts of the DMA buffer to be prefetched into the RAC. To >> avoid possible coherency problems, flush the RAC upon DMA completion. >> >> Signed-off-by: Kevin Cernekee <cernekee@xxxxxxxxx> >> Signed-off-by: Jaedon Shin <jaedon.shin@xxxxxxxxx> >> Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx> >> --- >> arch/mips/include/asm/bmips.h | 2 +- >> arch/mips/mm/dma-default.c | 15 +++++++++++++++ >> 2 files changed, 16 insertions(+), 1 deletion(-) > > I'm not keen on including platform-specific files that may blow up on > another platform. So what I suggest instead is something like rewriting > cpu_needs_post_dma_flush() to invoke a platform-specific hook function > plat_post_dma_flush() which would be defined in <asm/dma-coherence.h> > rsp. <mach/dma-coherence.h>. > > I'm going to whip up something. Hi Ralf, Regarding this patch: http://git.linux-mips.org/cgit/ralf/upstream-sfr.git/commit/?id=47df84c7341a4816b69b784b01fce304a15777a2 The same change is also needed for mach-bcm63xx (in-tree) and mach-brcmstb (out-of-tree). Somewhat confusingly, mach-bmips is a "Generic BMIPS kernel" but it isn't the only platform which uses BMIPS processors that have readahead caches. I am hoping that someday mach-bmips will have support for all mach-bcm63xx and mach-brcmstb platforms/peripherals, but we aren't quite there yet.
