On Sun, Mar 22, 2015 at 12:25:24PM +0100, Bert Vermeulen wrote: > It is bitbanging, at least on write. The hardware has a shift register that > is uses for reads. The generic spi for this board's architecture (ath79) > indeed uses spi-bitbang. > This "fast SPI" thing is what makes this one different: the boot flash and > MMC use regular SPI on the same bus as the CPLD. This CPLD needs this fast > SPI: a mode where it shifts in two bits per clock. The second bit is > apparently sent via the CS2 pin. Please make sure that all this is visible to someone looking at the driver, it's really not at all clear what's going on just from reading the code. > So I don't think spi-bitbang will do. I need to see about reworking things > to use less custom queueing -- I'm not that familiar with this yet. Mostly it's just a case of deleting the loops and using the core ones instead.
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