On Tue, 24 Feb 2015, Leonid Yegoshin wrote: > > SYNCI is only useful in non-SMP kernels. > Yes, until MIPS R6. I pressed hard on Arch team to change vague words in SYNCI > description and now (MIPS R6) it has words requiring execution on all cores: > > > "SYNCI globalization: > > Release 6: SYNCI globalization (as described below) is required: compliant > > implementations must globalize SYNCI. > > Portable software can rely on this behavior, and use SYNCI rather than > > expensive “instruction cache shootdown” > > using inter-processor interrupts." Good, thanks for enforcing sanity! > > If a thread is migrated to a different CPU between the SYNCI, and the > > attempt to execute the freshly generated code, the new CPU can still have a > > dirty ICACHE. So for Linux userspace, cacheflush(2) is your only option. Is it not a kernel bug then? Shouldn't migration code enforce cache coherency manually if hardware does not? User software is supposed to have a consistent view of the system and such details as being run on a multiprocessor should be completely hidden. Maciej
