On Tue, Feb 24, 2015 at 01:39:03PM -0800, Andrew Bresticker wrote: > It is the same sort of issue, though I think the only way to solve it > on MIPS would be to copy the image to the address it was linked at, > which could be problematic if there's overlap. There's also the cache > maintenance we'd have to do, which varies from CPU to CPU (and more so > the ARM I believe). On MIPS it's significantly less complex to implement than the in-kernel cache maintenance code because only one flush operation needs to be implemented that will be invoked only once so performance is less of an issue. Also oddball hardware such as the S-caches controlled by an external controller can be ignored for purpose of kernel decomporession. That pretty much leaves to treat the standard R4000 style of caches and a few oddballs like R2000 class processors. Ralf
