The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed. However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.
This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.
Reported-by: John Crispin <blogic@xxxxxxxxxxx>
Tested-by: Bruno Randolf <br1@xxxxxxxxxxx>
Signed-off-by: Manuel Lauss <manuel.lauss@xxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx [v3.17+]
---
John originally noticed that the reported UART baud base differed between 3.14
and 3.18 on the MTX1, Bruno tested and confirmed that the fix is correct.
Resend with linux mips ml address.
arch/mips/alchemy/common/clock.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index d8737a8..546914c 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -127,6 +127,8 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
t = 396000000;
else {
t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
+ if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
+ t &= 0x3f;
t *= parent_rate;
}
--
2.3.0
