On Tue, Feb 3, 2015 at 3:39 AM, Maciej W. Rozycki <macro@xxxxxxxxxxxxxx> wrote: > For the record -- the exact address `__fast_iob' reads from does not > really matter, all it has to guarantee is no side effects on read access. > Using the base of KSEG1 was therefore a natural choice for legacy MIPS > processors that set the architecture back at the time this code was added, > as the presence of exception vectors there guaranteed this area of the > address space behaved like RAM so the same location did for any system. > > With the introduction of revision 2 of the MIPS architecture the CP0 > EBase register was added and consequently there is no longer a guarantee > that exception vectors reside at the base of KSEG1. Using the value read > from CP0.EBase to determine a usable address might therefore be a better > idea, although the current revision of the MIPS architecture specification > that includes segmentation control makes it a bit complicated. Using a > dummy page mapped uncached instead might work the best. Would something like this work, assuming __fast_iob() doesn't get called before mem_init()? CKSEG1ADDR((void *)empty_zero_page) It is currently a GPL export, so maybe that would need to change to allow non-GPL drivers to use iob(). But that's still easier than allocating another dummy page.
