The Au1000 and Au1500 calculate the LRCLK a bit differently than
newer models: a single bit in MEM_STCFG0 selects if pclk is divided
by 4 or 5.
Signed-off-by: Manuel Lauss <manuel.lauss@xxxxxxxxx>
---
arch/mips/alchemy/common/clock.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 48a9dfc..428c9f0 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -315,17 +315,27 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
/* lrclk: external synchronous static bus clock ***********************/
-static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
{
- /* MEM_STCFG0[15:13] = divisor.
+ /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
+ * otherwise lrclk=pclk/4.
+ * All other variants: MEM_STCFG0[15:13] = divisor.
* L/RCLK = periph_clk / (divisor + 1)
* On Au1000, Au1500, Au1100 it's called LCLK,
* on later models it's called RCLK, but it's the same thing.
*/
struct clk *c;
- unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+ unsigned long v;
- v = (v & 7) + 1;
+ switch (t) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ v = 4 + ((alchemy_rdsmem(AU1000_MEM_STCFG0) >> 11) & 1);
+ break;
+ default: /* all other models */
+ v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+ v = (v & 7) + 1;
+ }
c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
pn, 0, 1, v);
if (!IS_ERR(c))
@@ -1060,7 +1070,7 @@ static int __init alchemy_clk_init(void)
ERRCK(c)
/* L/RCLK: external static bus clock for synchronous mode */
- c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
+ c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
ERRCK(c)
/* Frequency dividers 0-5 */
--
2.2.2
