On Tue, 20 Jan 2015, James Hogan wrote: > > While a preexisting bug, this is simply not true, there's CP0.Cause.TI to > > examine for a timer interrupt pending. Please fix your change to use > > `c0_compare_int_pending' instead and synchronise with stuff posted by > > James (cc-ed) at <http://patchwork.linux-mips.org/patch/8900/>. > > I'm not sure I follow what you mean. This change makes it treat r6 like > it treats r2 (i.e. there is still a Cause.TI bit), which sounds correct > to me. I'm guessing cpu_has_mips_r6 doesn't imply cpu_has_mips_r2. Correct, R6 is not backwards compatible with R2 so it doesn't set the R2 flag and consequently any compatibility that does exist has to be handled explicitly; see 28/70 for the details of the flag setup. Maciej
