On 01/16/2015 11:29 AM, Sergei Shtylyov wrote:
> Hello.
>
> On 1/16/2015 1:48 PM, Markos Chandras wrote:
>
>> From: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
>
>> MIPS R6 redefines several instructions and reduces the immediate
>> field to 9-bits so add related macros for the microassembler.
>
>> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
>> Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
>> ---
>> arch/mips/mm/uasm.c | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>
>> diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
>> index 4adf30284813..6596b6898637 100644
>> --- a/arch/mips/mm/uasm.c
>> +++ b/arch/mips/mm/uasm.c
> [...]
>> @@ -41,6 +42,8 @@ enum fields {
>> #define FUNC_SH 0
>> #define SET_MASK 0x7
>> #define SET_SH 0
>> +#define SIMM9_SH 7
>> +#define SIMM9_MASK 0x1ff
>>
>> enum opcode {
>> insn_invalid,
>> @@ -116,6 +119,14 @@ static inline u32 build_scimm(u32 arg)
>> return (arg & SCIMM_MASK) << SCIMM_SH;
>> }
>>
>> +static inline u32 build_scimm9(s32 arg)
>> +{
>> + WARN((arg > 0x1ff || arg < -0x200),
>
> Not 0xFF and -0x100? The values above don't fit into 9 bits...
Hi,
I think 0x1ff and -0x200 fit into 9-bits. Why do you think they don't?
--
markos
