Hello.
On 1/16/2015 1:49 PM, Markos Chandras wrote:
MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
[...]
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index bf82ec302cff..c084b38e727b 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -808,6 +808,17 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
}
regs->cp0_epc += 8;
break;
+ case cbcond0_op:
+ /* Only valid for MIPS R6 */
+ if (!cpu_has_mips_r6) {
+ ret = -SIGILL;
+ break;
+ }
+ /* Compact branches: bovc, beqc, beqzalc */
+ if (insn.i_format.rt && !insn.i_format.rs)
+ regs->regs[31] = epc + 4;
Hm, so this instruction doesn't have delay slot?
+ regs->cp0_epc += 8;
Then why 8 here?
WBR, Sergei
