Hi James,
On Fri, Jan 16, 2015 at 3:10 AM, James Hogan <james.hogan@xxxxxxxxxx> wrote:
> Commit 18743d2781d0 ("irqchip: mips-gic: Stop using per-platform mapping
> tables") in v3.19-rc1 changed the routing of IPIs through the GIC to go
> to the HW0 IRQ pin along with the rest of the GIC interrupts, rather
> than to HW1 and HW2 pins.
>
> This breaks SMP boot using the CMP or MT SMP implementations because HW0
> doesn't get unmasked when secondary CPUs are initialised so the IPIs
> will never interrupt secondary CPUs (nor any other interrupts routed
> through the GIC).
>
> Commit ff1e29ade4c6 ("MIPS: smp-cps: Enable all hardware interrupts on
> secondary CPUs") fixed this in advance for the CPS SMP implementation by
> unmasking all hardware interrupt lines for secondary CPUs, so lets do
> the same for the CMP and MT implementations.
>
> Fixes: 18743d2781d0 ("irqchip: mips-gic: Stop using per-platform mapping tables")
> Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
> Cc: Ralf Baechle <ralf@xxxxxxxxxxxxxx>
> Cc: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> Cc: Qais Yousef <qais.yousef@xxxxxxxxxx>
> Cc: linux-mips@xxxxxxxxxxxxxx
Reviewed-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> Note that CMP is still broken with Malta since the GIC driver now routes
> the local timer interrupt to a different IRQ pin to that expected by the
> CMP wait loop (see commit e9de688dac65 ("irqchip: mips-gic: Support
> local interrupts")), so the secondary CPU never completes its wait
> instruction to poll the LAUNCH_FGO flag, but that is a different issue.
I'm guessing this wait loop is in firmware? Should the GIC just leave
the timer IRQ routing alone then?
