Hello. On 01/07/2015 02:28 PM, Jayachandran C wrote:
Core configuration register IFU_BRUB_RESERVE has to be setup to handle a silicon errata which can result in a CPU hang.
Signed-off-by: Jayachandran C <jchandra@xxxxxxxxxxxx>
[...]
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S index 701c4bc..ff2673a 100644 --- a/arch/mips/netlogic/common/reset.S +++ b/arch/mips/netlogic/common/reset.S @@ -235,6 +235,24 @@ EXPORT(nlm_boot_siblings) mfc0 v0, CP0_EBASE, 1 andi v0, 0x3ff /* v0 <- node/core */ + /* Errata: to avoid potential live lock, only apply to 4 + * thread per core mode */
The preferred multi-line comment style is: /* * bla * bla */
+ andi v1, v0, 0x3 /* v1 <- thread id */ + bnez v1, 2f + nop
If this 'nop' is in a delay slot, there's a tradition to add extra space before the instruction.
+ + /* thread 0 of each core. */ + li t0, CKSEG1ADDR(RESET_DATA_PHYS)
Hm, does this get auto-expanded into several instructions?
+ lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ + subu t1, 0x3 /* 4-thread per core mode? */ + bnez t1, 2f + nop
Same here... WBR, Sergei
