On 12/19/2014 05:15 PM, David Daney wrote:
From: David Daney <david.daney@xxxxxxxxxx>
If we are generating TLB exception expecting separate vectors, we must
enable the feature.
Cc: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
Signed-off-by: David Daney <david.daney@xxxxxxxxxx>
---
Very lightly tested, but it seems to make my XI and RI tests work on
OCTEON II CPUs, which have the C0_Pagegrain[IEC] bit.
arch/mips/mm/tlb-r4k.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index e90b2e8..30639a6 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -489,6 +489,8 @@ static void r4k_tlb_configure(void)
#ifdef CONFIG_64BIT
pg |= PG_ELPA;
#endif
+ if (cpu_has_rixiex)
+ pg |= PG_IEC;
write_c0_pagegrain(pg);
}
David, I think it is still better to use set_c0_pagegrain() because
PageGrain has a lot of RW bits now and clear all of them may be not good.
