To flush to readahead cache, set 8th bit in the RAC_CONFIG.
The previous commit "MIPS: BMIPS: Flush the readahead cache after DMA"
has a problem overwriting to the original other configuration values.
Signed-off-by: Jaedon Shin <jaedon.shin@xxxxxxxxx>
---
arch/mips/mm/dma-default.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index ee6d12c..38ee47a 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -74,9 +74,11 @@ static inline int cpu_needs_post_dma_flush(struct device *dev)
boot_cpu_type() == CPU_BMIPS4350 ||
boot_cpu_type() == CPU_BMIPS4380) {
void __iomem *cbr = BMIPS_GET_CBR();
+ u32 cfg;
/* Flush stale data out of the readahead cache */
- __raw_writel(0x100, cbr + BMIPS_RAC_CONFIG);
+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
__raw_readl(cbr + BMIPS_RAC_CONFIG);
return 0;
--
1.9.3
