MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
---
arch/mips/include/uapi/asm/inst.h | 2 +-
arch/mips/kernel/branch.c | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 648addfe1e1c..b95363e0551f 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -21,7 +21,7 @@
enum major_op {
spec_op, bcond_op, j_op, jal_op,
beq_op, bne_op, blez_op, bgtz_op,
- addi_op, addiu_op, slti_op, sltiu_op,
+ addi_or_cbcond0_op, addiu_op, slti_op, sltiu_op,
andi_op, ori_op, xori_op, lui_op,
cop0_op, cop1_op, cop2_op, cop1x_op,
beql_op, bnel_op, blezl_op, bgtzl_op,
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index d9e3a0d72a64..cf390c76ba95 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -788,6 +788,12 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case lwc2_or_bc_op:
regs->cp0_epc += 8;
break;
+ case addi_or_cbcond0_op:
+ /* Compact branches: bovc, beqc, beqzalc */
+ if (insn.i_format.rt && !insn.i_format.rs)
+ regs->regs[31] = epc + 4;
+ regs->cp0_epc += 8;
+ break;
#endif
}
--
2.2.0
