Add new opcodes for the BC1EQZ and BC1NEZ instructions:
BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero
BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
---
arch/mips/include/uapi/asm/inst.h | 3 ++-
arch/mips/kernel/branch.c | 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index b7aa4c788983..648addfe1e1c 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -114,7 +114,8 @@ enum cop_op {
cfc_op = 0x02, mfhc_op = 0x03,
mtc_op = 0x04, dmtc_op = 0x05,
ctc_op = 0x06, mthc_op = 0x07,
- bc_op = 0x08, cop_op = 0x10,
+ bc_op = 0x08, bc1eqz_op = 0x09,
+ bc1nez_op = 0x0d, cop_op = 0x10,
copm_op = 0x18
};
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index ba68c005aeab..a6f7af2aa6ee 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -621,9 +621,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case bgtz_op:
case bgtzl_op:
- if (NO_R6EMU && insn.i_format.opcode == bgtzl_op)
+ if (NO_R6EMU && insn.i_format.opcode == bgtzl_op) {
/* not emulating the branch likely for R6 */
+ ret = -SIGILL;
break;
+ }
/* rt field assumed to be zero */
if ((long)regs->regs[insn.i_format.rs] > 0) {
epc = epc + 4 + (insn.i_format.simmediate << 2);
--
2.2.0
