The MIPS R6 JR instruction is an alias to the JALR one, so it may
needs emulation for non-R6 userlands.
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
---
arch/mips/kernel/branch.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index b7dd0926e87f..3df013ef7622 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -19,6 +19,9 @@
#include <asm/ptrace.h>
#include <asm/uaccess.h>
+static int mipsr2_emulation = 0;
+#define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation)
+
/*
* Calculate and return exception PC in case of branch delay slot
* for microMIPS and MIPS16e. It does not clear the ISA mode bit.
@@ -417,6 +420,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
regs->regs[insn.r_format.rd] = epc + 8;
/* Fall through */
case jr_op:
+ if (NO_R6EMU && insn.r_format.func == jr_op) {
+ ret = -SIGILL;
+ /* For R6, JR already emulated in jalr_op */
+ break;
+ }
regs->cp0_epc = regs->regs[insn.r_format.rs];
break;
}
--
2.2.0
