MIPS R6 changed the opcodes for LL/SC instructions and reduced the
offset field to 9-bits. This has some undesired effects with the "m"
constrain since it implies a 16-bit immediate. As a result of which,
add a register ("r") constrain as well to make sure the entire address
is loaded to a register before the LL/SC operations. Also use macro
to set the appropriate ISA for the asm blocks
Cc: Matthew Fortune <Matthew.Fortune@xxxxxxxxxx>
Signed-off-by: Markos Chandras <markos.chandras@xxxxxxxxxx>
---
arch/mips/include/asm/cmpxchg.h | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index eefcaa363a87..86a76f125bc8 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -38,15 +38,15 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
do {
__asm__ __volatile__(
- " .set arch=r4000 \n"
- " ll %0, %3 # xchg_u32 \n"
+ " .set "MIPS_ISA_ARCH_LEVEL" \n"
+ " ll %0, 0(%3) # xchg_u32 \n"
" .set mips0 \n"
" move %2, %z4 \n"
- " .set arch=r4000 \n"
- " sc %2, %1 \n"
+ " .set "MIPS_ISA_ARCH_LEVEL" \n"
+ " sc %2, 0(%3) \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
+ : "r" (m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
@@ -88,13 +88,13 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
do {
__asm__ __volatile__(
- " .set arch=r4000 \n"
- " lld %0, %3 # xchg_u64 \n"
+ " .set "MIPS_ISA_ARCH_LEVEL" \n"
+ " lld %0, 0(%3) # xchg_u64 \n"
" move %2, %z4 \n"
- " scd %2, %1 \n"
+ " scd %2, 0(%3) \n"
" .set mips0 \n"
: "=&r" (retval), "=m" (*m), "=&r" (dummy)
- : "R" (*m), "Jr" (val)
+ : "r" (m), "Jr" (val)
: "memory");
} while (unlikely(!dummy));
} else {
@@ -162,18 +162,18 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
- " .set arch=r4000 \n" \
- "1: " ld " %0, %2 # __cmpxchg_asm \n" \
+ " .set "MIPS_ISA_ARCH_LEVEL" \n" \
+ "1: " ld " %0, 0(%2) # __cmpxchg_asm \n" \
" bne %0, %z3, 2f \n" \
" .set mips0 \n" \
" move $1, %z4 \n" \
- " .set arch=r4000 \n" \
- " " st " $1, %1 \n" \
+ " .set "MIPS_ISA_ARCH_LEVEL" \n" \
+ " " st " $1, 0(%2) \n" \
" beqz $1, 1b \n" \
" .set pop \n" \
"2: \n" \
: "=&r" (__ret), "=R" (*m) \
- : "R" (*m), "Jr" (old), "Jr" (new) \
+ : "r" (m), "Jr" (old), "Jr" (new) \
: "memory"); \
} else { \
unsigned long __flags; \
--
2.2.0
