On 12/03/2014 03:55 PM, Leonid Yegoshin wrote:
On 12/03/2014 03:44 PM, David Daney wrote:
(...)
Big work
Not really, although by number of lines of code, it is about 3x the size
of your patch, it only touches the existing code in one place. It only
took about 3 days to write, adding full MIPS64 and R6 support would
probably be less than another week of work.
microMIPS I haven't looked at as we don't have anything to test it on.
but it doesn't support customized instructions,
GCC will never put these in the delay slot of a FPU branch, so it is not
needed.
multiple ASEs,
Same as above. But any instructions that are deemed necessary can
easily be added.
MIPS R6
It is a proof of concept. R6 can easily be added if needed.
Your XOL emulation doesn't handle R6 either, so this is no worse than
your patch in that respect.
etc.
GCC will never put trapping instructions in the delay slot either.
All we have to support are non-trapping and non-branch/jump instructions
from the ISA manuals that can be executed from userspace processes.
That makes it slightly simpler than complete ISA emulation.
Well, it is still not a replacement of XOL emulation.
For use by the FPU emulator, it is probably good enough
Even close.
I disagree, that is why I took the time to do it.
