> Fix the 74K D-cache alias erratum workaround so that it actually works.
> Our current code sets MIPS_CACHE_VTAG for the D-cache, but that flag
> only has any effect for the I-cache. Additionally MIPS_CACHE_PINDEX is
> set for the D-cache if CP0.Config7.AR is also set for an affected
> processor, leading to confusing information in the bootstrap log (the
> flag isn't used beyond that).
> So delete the setting of MIPS_CACHE_VTAG and rely on MIPS_CACHE_ALIASES,
> set in a common place, removing I-cache coherency issues seen in GDB
> testing with software breakpoints, gdbserver and ptrace(2), on affected
> systems.
> While at it add a little piece of explanation of what CP0.Config6.SYND
> is so that people do not have to chase documentation.
This shift to MIPS_CACHE_ALIASES is not needed, a use of MIPS_CACHE_VTAG
in dcache is actually a way how to prevent some very specific situations
in 74K(E77)/1074K(E17) cache handling. It is not a case of cache
aliasing and name VTAG is used because it is related with virtual
address conversion tagging. I reused MIPS_CACHE_VTAG just to save some
spare bits in cpu_info.options and because D-cache never had virtual
tagging like I-cache.
The setting d-cache aliases then CPU hasn't it is a significant
performance loss and should be avoided.
Please don't use this patch.
- Leonid.
