Hello. On 10/10/2014 12:07 AM, John Crispin wrote:
Describe gpio-rt2880 binding.
Signed-off-by: John Crispin <blogic@xxxxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx Cc: devicetree@xxxxxxxxxxxxxxx Cc: linux-gpio@xxxxxxxxxxxxxxx --- .../devicetree/bindings/gpio/gpio-rt2880.txt | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-rt2880.txt
diff --git a/Documentation/devicetree/bindings/gpio/gpio-rt2880.txt b/Documentation/devicetree/bindings/gpio/gpio-rt2880.txt new file mode 100644 index 0000000..b4acf02 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-rt2880.txt @@ -0,0 +1,40 @@ +Ralink SoC GPIO controller bindings + +Required properties: +- compatible: + - "ralink,rt2880-gpio" for Ralink controllers +- #gpio-cells : Should be two. + - first cell is the pin number + - second cell is used to specify optional parameters (unused) +- gpio-controller : Marks the device node as a GPIO controller +- reg : Physical base address and length of the controller's registers +- interrupt-parent: phandle to the INTC device node
It's not a required property, it can be inherited from the nodes above.
+- interrupts : Specify the INTC interrupt number +- ralink,num-gpios : Specify the number of GPIOs +- ralink,register-map : The register layout depends on the GPIO bank and actual + SoC type. Register offsets need to be in this order. + [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
This should be determined by the "compatible" property alone, I think.
+ +Optional properties: +- ralink,gpio-base : Specify the GPIO chips base number
WBR, Sergei
